Title
Napredni metodi projektovanja digitalnih integrisanih kola u nanometarskim tehnologijama sa posebnim naglaskom na brzinu, statičku i dinamičku potrošnju
Creator
Jovanović, Borisav D.
Copyright date
2015
Object Links
Select license
Autorstvo 3.0 Srbija (CC BY 3.0)
License description
Dozvoljavate umnožavanje, distribuciju i javno saopštavanje dela, i prerade, ako se navede ime autora na način odredjen od strane autora ili davaoca licence, čak i u komercijalne svrhe. Ovo je najslobodnija od svih licenci. Osnovni opis Licence: http://creativecommons.org/licenses/by/3.0/rs/deed.sr_LATN Sadržaj ugovora u celini: http://creativecommons.org/licenses/by/3.0/rs/legalcode.sr-Latn
Language
Serbian
Cobiss-ID
Theses Type
Doktorska disertacija
description
Datum odbrane: 03.03.2016.
Other responsibilities
mentor
Petković, Predrag 1954-
član komisije
Damnjanović, Milunka
član komisije
Jevtić, Milun 1950-
član komisije
Milovanović, Dragiša 1951-
član komisije
Živanović, Miloš 1948-
Academic Expertise
Tehničko-tehnološke nauke
University
Univerzitet u Nišu
Faculty
Elektronski fakultet
Group
Katedra za elektroniku
Alternative title
The advanced methods for digital integrated circuit design in nanometer technologies, with special emphasis on speed, static and dynamic consumption
Publisher
[B. D. Jovanović]
Format
[11], IV, 114 listova
description
Biobibliografski podaci: listovi 94-110
description
Electronics
Abstract (en)
Advanced methods for digital circuit design, based on modern nanoscale technologies,
are applied to a novel SoC microcontroller design with the industry standard 8051 instruction
set. The power consumption of the proposed IP cores and the effects of utilization of both
static and dynamic power minimization techniques will be examined using following process
technologies: CMOS 350 nm, 90 nm and 65 nm. The static power saving methodologies
which include shutting down any inactive digital block, reduction of supply voltage and
utilization of different standard cell libraries, allows for significant improvements in energy
efficiency.
Authors Key words
Dynamic and static dissipation power, low power techniques, microcontroller, faulttolerances,
IP block
Authors Key words
statička i dinamička snaga disipacije CMOS kola, tehnike za smanjenje snage,
mikrokontroler, pouzdanost rada sistema, IP blok
Classification
(621.3.049.77+004.087.5):004.9
Subject
621.3.049.77+004.087.5]:004.9(043.3)
Type
Elektronska teza
Abstract (en)
Advanced methods for digital circuit design, based on modern nanoscale technologies,
are applied to a novel SoC microcontroller design with the industry standard 8051 instruction
set. The power consumption of the proposed IP cores and the effects of utilization of both
static and dynamic power minimization techniques will be examined using following process
technologies: CMOS 350 nm, 90 nm and 65 nm. The static power saving methodologies
which include shutting down any inactive digital block, reduction of supply voltage and
utilization of different standard cell libraries, allows for significant improvements in energy
efficiency.
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